Anisotropic material damage process for etching low-k dielectric materials

ABSTRACT

A device includes a first dielectric material and a plurality of conductive lines disposed in the first dielectric material. Each of the plurality of conductive lines includes a conductive fill material and a liner layer disposed between at least a bottom surface of the conductive fill material and the first dielectric material. The first dielectric material defines at least one air gap between two of the plurality of conductive lines. The at least one air gap has a first depth greater than a second depth of the plurality of conductive lines.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosed subject matter relates generally to the fabrication ofsemiconductor devices, and, more particularly, to an anisotropicmaterial damage process for etching low-k dielectric materials.

2. Description of the Related Art

In modern integrated circuits, minimum feature sizes, such as thechannel length of field effect transistors, have reached the deepsub-micron range, thereby steadily increasing performance of thesecircuits in terms of speed and/or power consumption and/or diversity ofcircuit functions. As the size of the individual circuit elements issignificantly reduced, thereby improving, for example, the switchingspeed of the transistor elements, the available floor space forinterconnect lines electrically connecting the individual circuitelements is also decreased. Consequently, the dimensions of theseinterconnect lines and the spaces between the metal lines have to bereduced to compensate for a reduced amount of available floor space andfor an increased number of circuit elements provided per unit area.

In such modern integrated circuits, a limiting factor of deviceperformance is the signal propagation delay caused by the switchingspeed of the transistor elements. As the channel length of thesetransistor elements has now reached 50 nm and less, the signalpropagation delay is no longer limited by the field effect transistors.Rather, the signal propagation delay is limited, owing to the increasedcircuit density, by the interconnect lines, since the line-to-linecapacitance (C) is increased and also the resistance (R) of the lines isincreased due to their reduced cross-sectional area. The parasitic RCtime constants and the capacitive coupling between neighboring metallines, therefore, require the introduction of a new type of material forforming the metallization layer.

Traditionally, metallization layers, i.e., the wiring layers includingmetal lines and vias for providing the electrical connection of thecircuit elements according to a specified circuit layout, are formed bya dielectric layer stack including, for example, silicon dioxide and/orsilicon nitride, with aluminum as the typical metal. Since aluminumsuffers from significant electromigration at higher current densitiesthat may be necessary in integrated circuits having extremely scaledfeature sizes, aluminum is being replaced by, for instance, copper,which has a significantly lower electrical resistance and a higherresistivity against electromigration. For highly sophisticatedapplications, in addition to using copper and/or copper alloys, thewell-established and well-known dielectric materials silicon dioxide(k≈4.2) and silicon nitride (k>7) may increasingly be replaced byso-called low-k dielectric materials having a relative permittivity ofapproximately 3.0 and less. However, the transition from the well-knownand well-established aluminum/silicon dioxide metallization layer to acopper-based metallization layer possibly in combination with a low-kdielectric material is associated with a plurality of issues to be dealtwith.

For example, copper may not be deposited in relatively high amounts inan efficient manner by well-established deposition methods, such aschemical and physical vapor deposition. Moreover, copper may not beefficiently patterned by well-established anisotropic etch processes.Therefore, the so-called damascene or inlaid technique is frequentlyemployed in forming metallization layers including copper lines andvias. Typically, in the damascene technique, the dielectric layer isdeposited and then patterned for receiving trenches and via openingsthat are subsequently filled with copper or alloys thereof by platingmethods, such as electroplating or electroless plating. Moreover, sincecopper readily diffuses in a plurality of dielectrics, such as silicondioxide and in many low-k dielectrics, the formation of a diffusionbarrier layer at interfaces with the neighboring dielectric material maybe required.

Moreover, the diffusion of moisture and oxygen into the copper-basedmetal has to be suppressed as copper readily reacts to form oxidizedportions, thereby possibly deteriorating the characteristics of thecopper-based metal line with respect to adhesion, conductivity and theresistance against electromigration.

During the filling in of a conductive material, such as copper, into thetrenches and via openings, a significant degree of overfill has to beprovided in order to reliably fill the corresponding openings frombottom to top without voids and other deposition-related irregularities.Consequently, after the metal deposition process, excess material mayhave to be removed and the resulting surface topography is to beplanarized, for instance, by using electrochemical etch techniques,chemical mechanical polishing (CMP) and the like. For example, duringCMP processes, a significant degree of mechanical stress may be appliedto the metallization levels formed so far, which may cause structuraldamage to a certain degree, in particular when sophisticated dielectricmaterials of reduced permittivity are used. As previously explained, thecapacitive coupling between neighboring metal lines may have asignificant influence on the overall performance of the semiconductordevice, in particular in metallization levels, which are substantially“capacitance driven,” i.e., in which a plurality of closely spaced metallines have to be provided in accordance with device requirements,thereby possibly causing signal propagation delay and signalinterference between neighboring metal lines. For this reason, so-calledlow-k dielectric materials or ultra-low-k (ULK) materials may be used,which may provide a dielectric constant of 3.0 and significantly less inorder to enhance the overall electrical performance of the metallizationlevels. On the other hand, typically, a reduced permittivity of thedielectric material is associated with a reduced mechanical stability,which may require sophisticated patterning regimes so as to not undulydeteriorate reliability of the metallization system.

The continuous reduction of the feature sizes, however, with gatelengths of approximately 40 nm and less, may demand for even morereduced dielectric constants of the corresponding dielectric materials.For this reason, it has been proposed to introduce “air gaps,” at leastat critical device areas, since air or similar gases may have adielectric constant of approximately 1.0.

Air gaps may be formed by etching the dielectric material of themetallization layer under consideration selectively with respect to themetal lines down to a specified depth. Consequently, a self-alignedtechnique may be accomplished by using the etch selectivity between themetal lines and the low-k or ULK dielectric material. However, etchingprocesses for low-k and ULK materials are complex. A conventional etchprocess employs a reactive ion plasma etch process (e.g., using NH₃).Although the reactive ion etch is somewhat self-aligned, there is ananisotropic component that has a propensity to result in under-cuttingof the metal lines when the etch is performed. In addition, the reactiveion plasma etch process can damage a cap layer formed above the metallines to prevent electromigration of the metal into the dielectricmaterial, thereby causing reliability issues at the interface betweenthe metal line and the cap layer. In the corner regions of the metallines, the cap layer covers edges of a liner layer surrounding the metalline. Damage to the cap layer can result in corner rounding andadditional reliability issues arising from defects introduced into theliner.

The present application is directed to various methods for forming airgaps in metal line structures so as to eliminate or reduce the effectsof one or more of the problems identified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure is directed to semiconductor devicesincluding air gaps. According to one embodiment, a device includes afirst dielectric material and a plurality of conductive lines disposedin the first dielectric material. Each of the plurality of conductivelines includes a conductive fill material and a liner layer disposedbetween at least a bottom surface of the conductive fill material andthe first dielectric material. The first dielectric material defines atleast one air gap between two of the plurality of conductive lines. Theat least one air gap has a first depth greater than a second depth ofthe plurality of conductive lines.

Another illustrative device includes a first dielectric material and aplurality of conductive lines disposed in the first dielectric material,Each of the conductive lines includes a liner layer disposed between atleast a bottom surface of a conductive fill material and the firstdielectric material. A first cap layer is disposed above the pluralityof conductive lines. The first cap layer covers top surfaces of theconductive fill material and edges of the liner layer. The firstdielectric material defines at least one air gap between two of theplurality of conductive lines. The at least one air gap has a firstdepth greater than a second depth of the plurality of conductive lines.A second cap layer is disposed above the plurality of conductive linesand in an upper portion of the at least one air gap.

Yet another illustrative device includes a first dielectric material anda plurality of conductive lines disposed in the first dielectricmaterial. Each of the conductive lines includes a conductive fillmaterial and a liner layer disposed between at least a bottom surface ofthe conductive fill material and the first dielectric material. Thefirst dielectric material defines at least one air gap between two ofthe plurality of conductive lines. The at least one air gap has a firstdepth greater than a second depth of the plurality of conductive lines.A first cap layer lines the at least one air gap.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIGS. 1A-1K are cross-sectional diagrams depicting illustrativetechniques for forming an air gap structure using a reactant photonexposure and etch process.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase. The present disclosure is directed to various methods offorming an air gap structure. With reference to the attached drawingsvarious illustrative embodiments of the methods and devices disclosedherein will now be described in more detail.

FIGS. 1A-1K are cross-sectional diagrams illustrating a method forforming an air gap structure in a semiconductor device 100, which, inthe present embodiment, may be represented by an integrated circuitincluding circuit elements, such as transistors, capacitors, resistorsand the like. FIG. 1A illustrates the device 100 including a devicelevel (not shown) formed in and above a substrate 105 in whichsemiconductor-based circuit elements may be provided. For convenience,any such circuit elements are not shown in FIG. 1A. The substrate 105may also include any appropriate microstructure features, such asmicro-mechanical components, optoelectronic components and the like,wherein at least some of these components may require an interconnectstructure formed in a metallization system 110. In highly complexintegrated circuits, a very large number of electrical connections maybe required and, thus, a plurality of metallization layers 115, 120 maytypically be formed in the metallization system 110. For example, themetallization layers 115, 120 may represent two of a plurality ofmetallization layers of the system 110, each of which may connect to alower-lying metallization layer in accordance with the required overallcircuit layout. In other cases, the layer 115 of the metallizationsystem 110 may represent a contact structure which may includeappropriate contact elements, for instance partially formed on the basisof a metal-containing material, in order to connect to semiconductordevices in the device layer. In this case, the metallization layer 115may be considered as the very first metallization layer, while the layer120 may be considered as an interface connecting the metallizationsystem 110 with the actual circuit elements formed in and above thesubstrate 105.

The metallization layer 115 may comprise a dielectric material 125,which may be provided in the form of any appropriate material, such as alow-k dielectric material, a dielectric material having a dielectricconstant of approximately 2.7 or higher or an ultra-low-k (ULK)material, a dielectric material having a dielectric constant ofapproximately 2.5 or lower. The metallization layer 120 includes a layer130 (e.g., SiCN or SiN) and a dielectric material 135, which may besimilar to the dielectric material 125 in the metallization layer 115.

FIG. 1B illustrates the device 100 after a patterned hard mask layer 140(e.g., (TiN, TEOS, SiN, etc.) is formed above the dielectric material135. The hard mask layer 140 may be formed by depositing a hard maskmaterial, forming a photoresist layer above the hard mask material,patterning the photoresist layer using a photolithography process, andetching the hard mask material exposed by the patterned photoresistlayer to define openings 145.

FIG. 1C illustrates the device after a reactant photon exposure process150 is performed to generate damaged regions 137 in the dielectricmaterial 135. The reactant photon exposure process 150 includesproviding an ambient including a carbon gettering agent (CGA) andconcurrently illuminating the device 100 with a radiation source, suchas a UV or VUV radiation source. In general, the photons from theradiation source disrupt bonds in the dielectric material 135, therebyproviding unattached carbon groups (e.g., methyl groups). The CGAmolecules react with the carbon groups and prevent the bonds fromreforming and allow the gettered carbon to exit the film, resulting incarbon depletion in the exposed portions of the dielectric material 135.As a result of this carbon gettering, the damaged (carbon-depleted)portions 137 of the dielectric material 135 become soluble in a wet etchsolution. In the illustrated embodiment, the CGA may be oxygen gas (O₂),ammonia gas (NH₃), or some other gas that may react with the carbongroups liberated by the radiation and preventing the bonds with thecarbon groups from reforming. The photons may be collimated so as toreduce the likelihood of scattering. Because, the carbon getteringprocess only occurs in regions exposed to the collimated radiation, thereactant photon exposure process 150 is highly anisotropic, as comparedto a reactant ion plasma etch process that has a higher relative degreeof scattering of damaging species (ions, radicals). The depth of therecesses 152 may be controlled based on the photon dose (exposureintensity and time), and resulting penetration depth, of the radiation.

FIG. 1D illustrates the device 100 after performing a wet etch process(e.g., HF) to remove the damaged portions 137 of the dielectric material135 to form recesses 152.

FIG. 1E illustrates the device 100 after several processes are performedto form conductive lines 155A, 155B in the recesses 152. A multiplestage fill process forms a liner layer 160 (e.g., TaN, TiN, Ta, etc.) inthe recesses 152, followed by a metal fill material 165 (e.g., copper)to overfill the recesses 152. A planarization process removes theoverfill, and the hard mask layer 140. A cap layer 170 (e.g., AlN or Co)is formed above the metal fill material 165 and the edges of the linerlayer 160. The liner layer 160 and the cap layer 170 prevent diffusionof the metal fill material 165 into the dielectric material 135. The caplayer 170 also serves to protect the metal fill material 165 duringsubsequent processing steps.

FIG. 1F illustrates the device 100 after a cap layer 175 (e.g., SiCN) isformed above the dielectric material 135 and a patterned hard mask layer180 is formed above selected metal lines 155A. The hard mask layer 180may include a stack of layers, such as a stack including an organicpolymer, SiNCH, TEOS and SiON. The hard mask layer 180 may be patternedusing a photoresist layer and one or more etch processes to remove thevarious layers in the stack, whereby the etch processes are terminatedupon exposing the cap layer 175. FIG. 1G illustrates the device 100after an etch process is performed to remove the cap layer 175 notcovered by the hard mask layer 180 (i.e., above the lines 155B) andanother etch process is performed to remove the hard mask layer 180.

FIG. 1H illustrates the device 100 after a second reactant photonexposure process 185 is performed to generate damaged portions 187 inthe dielectric material 135. Again, the reactant photon exposure process185 includes providing an ambient including a carbon gettering agent(CGA) and illuminating the device 100 with a radiation source, such as aUV or VUV radiation source. The use of AlN prevents damage to the Cuwhen O₂ is used as the CGA, and the use of NH₃ as the CGA preventsdamage to the Cu if it is uncapped or to Co if it is used as a caplayer.

FIG. 11 illustrates the device 100 after performing a wet etch process(e.g., HF) to remove the damaged portions 187 of the dielectric material135 to form recesses 188 between the metal lines 155B.

During the second reactant photon exposure process 185, the metal lines155B embedded in the dielectric material 135 act as a mask layer to theprocess 185, thus allowing the recesses 188 to be substantiallyself-aligned between the metal lines 155B. Furthermore, due to theenhanced anisotropy of the reactant photon exposure process 185, thedepth of the recesses 188 may be greater than the depth of the metallines 155B without substantially undercutting the metal lines 155B.Moreover, because there is no particle bombardment in the reactantphoton exposure process 185, surface damage to the cap layer 170 on themetal lines 155B is also reduced as compared to a reactive ion plasmaetch process.

FIG. 1J illustrates the device 100 after a conformal deposition processis performed to form a cap layer 190 (e.g., SiCN) above the metal lines155B. The cap layer 190 does not completely fill the recesses 188,thereby creating an air gap between the metal lines 155B.

FIG. 1K illustrates the device 100 after additional dielectric material195 is formed above the metal lines 155A, 155B. The dielectric material195 may be similar to the dielectric material 135.

The techniques for forming an air gap structure described herein havenumerous advantages. Because the etch processes for patterning thedielectric material 135 do not include a reactive ion bombardmentcomponent, the damage to surrounding structures or layers is minimized.Also, the depth of the air gap can be increased to improve the operatingcharacteristics of the device 100.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

What is claimed:
 1. A device, comprising: a first dielectric material;and a plurality of conductive lines disposed in said first dielectricmaterial, wherein said plurality of conductive lines each comprises aconductive fill material and a liner layer disposed between at least abottom surface of said conductive fill material and said firstdielectric material, said first dielectric material defines at least oneair gap between two of said plurality of conductive lines, and said atleast one air gap has a first depth greater than a second depth of saidplurality of conductive lines.
 2. The device of claim 1, furthercomprising a first cap layer disposed above said conductive lines. 3.The device of claim 2, further comprising a second dielectric layerdisposed above said first cap layer.
 4. The device of claim 2, furthercomprising a second cap layer disposed above said conductive fillmaterial and in an upper portion of said at least one air gap.
 5. Thedevice of claim 4, wherein said second cap layer comprises aluminumnitride.
 6. The device of claim 4, wherein said second cap layercomprises cobalt.
 7. The device of claim 4, wherein said first cap layercovers edges of said liner layer.
 8. The device of claim 4, wherein saidsecond cap layer lines said at least one air gap.
 9. The device of claim1, wherein said plurality of conductive lines comprise copper.
 10. Adevice, comprising: a first dielectric material; a plurality ofconductive lines disposed in said first dielectric material, whereinsaid plurality of conductive lines each comprises a liner layer disposedbetween at least a bottom surface of a conductive fill material and saidfirst dielectric material; a first cap layer disposed above saidplurality of conductive lines, wherein said first cap layer covers topsurfaces of said conductive fill material and edges of said liner layer,said first dielectric material defines at least one air gap between twoof said plurality of conductive lines, and said at least one air gap hasa first depth greater than a second depth of said plurality ofconductive lines; and a second cap layer disposed above said pluralityof conductive lines and in an upper portion of said at least one airgap.
 11. The device of claim 10, wherein said second cap layer comprisesaluminum nitride.
 12. The device of claim 10, wherein said second caplayer comprises cobalt.
 13. The device of claim 10, wherein said secondcap layer lines said at least one air gap.
 14. The device of claim 10,wherein said plurality of conductive lines comprise copper.
 15. Adevice, comprising: a first dielectric material; a plurality ofconductive lines disposed in said first dielectric material, whereineach of said plurality of conductive lines comprises a conductive fillmaterial and a liner layer disposed between at least a bottom surface ofsaid conductive fill material and said first dielectric material, saidfirst dielectric material defines at least one air gap between two ofsaid plurality of conductive lines, and said at least one air gap has afirst depth greater than a second depth of said plurality of conductivelines; and a first cap layer lining said at least one air gap.
 16. Thedevice of claim 15, further comprising a second cap layer disposed abovesaid plurality of conductive lines, wherein a portion of said first caplayer is disposed above a portion of said second cap layer.
 17. Thedevice of claim 16, wherein said second cap layer covers edges of saidliner layer.
 18. The device of claim 15, wherein said first cap layercomprises aluminum nitride.
 19. The device of claim 15, wherein saidfirst cap layer comprises cobalt.
 20. The device of claim 15, whereinsaid plurality of conductive lines comprise copper.